> For the complete documentation index, see [llms.txt](https://docs.caetron.io/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.caetron.io/product-documentation/helot-bms100-series-manual/internal-circuits.md).

# Internal Circuits

## Power, CAN Block Diagram

The Helot modules contain transient voltage suppression and reverse polarity protection. An internal fuse is included between the +VSUPPLY bus and the module power circuitry to reduce the risk of a faulty module taking down the entire bus and other connected devices.

<figure><img src="/files/CP2tMtimqP0wqsSMtzXr" alt=""><figcaption><p>BMS100 - Power, CAN Block Diagram</p></figcaption></figure>

## Isolation Block Diagram

The modules are designed to provide 1kV of isolation between the Power, CAN Interface (J2/J3) and the Battery Cell Interface (J1). This isolation is implemented with two digital isolators spanning the GND and IGND references, between the MCU and Battery ASIC.

<figure><img src="/files/siKdkYv5QJjUr8oAfOcQ" alt=""><figcaption><p>BMS100 - Isolation Block Diagram</p></figcaption></figure>

## Balancing Front-end Circuit Diagram

All cell tap interfaces are fused ([Bel Fuse C2Q-250](https://www.belfuse.com/product/part-details?partn=C2Q-250)) to mitigate the risk of cell damage in the event of an internal module failure or short circuit. 47 Ohm, automotive grade pulse withstanding resistors are used for dissipative shunting of cell currents.

<figure><img src="/files/1jIP3IYAvjwAAJGVND7E" alt="" width="563"><figcaption><p>BMS100 - Balancing Front-end Circuit Diagram</p></figcaption></figure>

## NTC Input Circuit Diagram

The internal Battery ASIC provides a switched +2.5V reference bias, via a 10K pull-up for each of the two (2) external NTC temperature sensors.

{% hint style="warning" %}
Never injected voltage into the VTEMP pins, as it may damage the internal circuitry.
{% endhint %}

<figure><img src="/files/BqJ8LPlmbbTZKRfJnNBS" alt="" width="563"><figcaption><p>BMS100 - NTC Input Circuit Diagram</p></figcaption></figure>


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